Lighter and thinner computing platforms are being designed, driving a reduction of package thickness, including both IC chip, or die, thickness and package substrate thickness. Concurrently, greater reliance on Internet data storage and cloud computing is driving server computers toward larger die sizes. For example, for a packaged processor may house a silicon die of approximately 33×22 mm. During packaging, thinner and/or larger die suffer greater die deflection at a given solder reflow temperature. A thinner package substrate, non-uniform metallization density across the substrate stack-up, and larger area all act to increase the substrate deflection. Therefore, gaps between the die and a package substrate may increase during chip attach process (module), resulting in more non-contact open (NCO) failures, thus impacting the assembly yield.
Various solutions are being researched to improve the chip attach yield. Glass cloth in buildup layers, for example, may be employed to reduce the substrate deflection during chip attach reflow. Bump flattening may also be employed to reduce incoming package deflection and facilitate better contact between solder bumps and die bumps in order to improve chip attach yield. High modulus core materials have also been investigated for package substrates, but these materials possess uncertainty with respect to package reliability and pose an issue for electrical signal integrity if placed near routing layers within substrate. All these methods add processing cost to the substrate and have thus far not succeeded in completely eliminating NCO yield loss with NCO often still posing the greatest yield loss issue.
A robust solution providing significant margin for NCO that can be implemented easily across multiple products without adding significant substrate cost is therefore advantageous.